1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a layout structure for a semiconductor memory device having a hierarchical structure and a layout method therefor.
A claim of priority under 35 U.S.C. §119 is made to Korean Patent Application 10-2005-29369, filed on Apr. 8, 2005, the content of which is hereby incorporated by reference in its entirety.
2. Description of the Related Art
In general, as semiconductor device integration has recently improved, the number of memory cells per semiconductor device has increased and the size of memory cells has been reduced. Consequently, the length and the number of word lines and bit lines connected with the memory cells has also increased. Such an increase causes word line and bit line capacitance to increase, which consequently increases power consumption and reduces operation speed of semiconductor memory devices. Thus, for 64M DRAM and 256M DRAM, a hierarchical concept has been introduced for layout of circuits and wires, in view of the recognition that high speed operation and a low power consumption are restricted by chip size increase in a conventional structure of word lines and bit lines.
In a semiconductor memory device having a general hierarchical structure, a global bit line (or a main bit line or master bit line), a local bit line (or a sub bit line or slave bit line), a global word line (or main word line) and a local word line (or sub word line) etc., are disposed at different conductive layers. In particular, an example of hierarchical structure of bit lines and/or word lines for a DRAM (Dynamic Random Access Memory) is disclosed in U.S. Pat. No. 6,069,815.
Meanwhile, as another approach to realize high performance and low power consumption, next-generation memory devices are being developed that do not have refresh operations, in contrast to semiconductor memory devices such as volatile DRAM. An example of such a next-generation memory device is a PRAM (Phase change Random Access Memory), which uses phase change material. A phase change material such as chalcogenide has a resistance that changes responsive to phase change of the material caused by temperature. For example, GexSbyTez (hereinafter, referred to as ‘GST′’) as an alloy of Ge (germanium), Sb (antimony) and Te (tellurium) is generally used as a phase change material. The phase change material is useful in semiconductor memory devices, because the phase thereof can be rapidly changed to an amorphous state or a crystalline state by temperature. The phase change material has a high resistance in an amorphous state, and has a low resistance in a crystalline state, whereby the amorphous state of the phase change material is defined as a ‘reset’ or logic ‘1’ state, and the crystalline state is defined as a ‘set’ or logic ‘0’ state. However, the states may be defined vice-versa when applied to semiconductor memory devices.
Memory cells constituting the PRAM described above may be formed as either a transistor structure and a diode structure. The transistor structure is a memory cell structure wherein the phase change material is connected to an access transistor in series. The diode structure is a memory cell structure wherein the phase change material is connected to a diode in series. Examples of PRAM employing memory cells of the transistor structure and the diode structure are disclosed in U.S. Pat. No. 6,760,017.
In a memory cell structure, a PRAM employing a diode structure can have a large write current that increases exponentially applied thereto as a function of voltage, as compared to a PRAM employing a transistor structure. By using a diode structure which is generally smaller than a transistor structure, a merit of flexibility for size reduction of memory cells and the overall chip is realized. Accordingly, in a semiconductor memory device requiring high integration, high-speed and low-power consumption, the use of PRAM employing memory cells of diode structure is expected to increase.
FIG. 1 illustrates a general PRAM memory cell structure having a diode structure. Referring to FIG. 1, a memory cell 50 of the PRAM is constructed of one diode D and one variable resistant element GST, wherein the variable resistant element GST is formed of phase change material as described above. The diode D of the memory cell 50 is connected between a word line WL and the variable resistant element GST, and has a cathode terminal connected to the word line WL and an anode terminal connected to one end of the variable resistant element GST. Another end of the variable resistant element GST is connected to a bit line BL.
In a semiconductor memory device having such a structure and employing memory cells of the diode structure, the variable resistant element GST is used as a data storage element. A write operation is performed by using a reversible characteristic of the variable resistant element GST based on magnitude of current and voltage source applied to memory cells through the bit line BL. To perform the write operation in memory cell 50, current is supplied through the bit line BL. The word line WL is transited to a low level or ground level, so that a forward bias is applied to the diode D, forming a current path along a direction from the bit line BL to the word line WL. At this time, a phase change occurs in the variable resistant element GST connected to the anode terminal of the diode D, to thus place the variable resistant element GST in a ‘set’ state of low resistance or a ‘reset’ state of high resistance.
During a read operation, data stored in the variable resistant element GST is determined by the volume of current flowing through memory cells as responsive to the memory cell being in the ‘set’ or ‘reset’ state. In other words, when the variable resistant element GST within a memory cell is in a ‘reset’ state, the memory cell has a high resistance value, thus current of little volume flows from bit line BL having a given level. When the variable resistant element GST has a ‘set’ state, the memory cell has a low resistance value, and relatively higher current of greater volume flows.
A PRAM having memory cells of diode structure offer increasingly high integration and performance, with low-power consumption. Accordingly, it is expected that a hierarchical concept be necessarily introduced to a layout of wires formed on memory cells in the PRAM of the diode structure. In such a hierarchical structure, bit lines BL and word lines WL are hierarchically disposed in the configuration of memory cells having the same size as described above, thereby obtaining smaller size chips and providing an advantage of high performance.
In a PRAM having memory cells of transistor structure, the structure is similar to a structure of general DRAM, except that the storage element is a variable resistant element. Thus, a hierarchical wire layout for PRAM of transistor structure is equal or similar to that of DRAM. In contrast, in a PRAM having memory cells of diode structure, the memory cell structure is definitely different from DRAM, and thus a correspondingly appropriate hierarchical layout of wires should be developed.